Відео

Amazing, thanks for bringing this topic to the light and discussing on it!

Possible to re-upload without the picture flashing? Thanks

One of the best accelerate NIC hardware on FPGA presentation I've heard for free

Where can I get a Sonata board?

Can SystemRDl support SystemC Verifcatoin Constraint from the SCV package? And then generate the SystemC header file including the constraint where the registers are described as Struct or Classes?

Boss, Your videos are very good, but please rename them with correct order.

Wonderful stuff!

your research is important to keep us not being enslaved remember we need a open source standard to have a new monetary system that's not controlled by the world Elites

I trying to find Renode Emu Tutorial

This is so cool. I had actually read that very paper on wave pipelining, but didn't consider it practical (for all the reasons you cite). That fact you pulled it off and on an FPGA to boot, is impressive. Re. the audience comment: self timed logic is interesting too, but is completely different; wave pipelining is overhead-free, where as self-timed logic has buffers for each "wave". The main difference from synchronous is that the clock is effectively local to each stage (which has its own pros and cons).

Really a nice presentation. But the demo seems not work through the command provided.

This looks a lot like Cadence ADE Assembler. It seems like I'm going to have to take some time and do some analog/mixed-signal design with the open tools!

Great presentation by the tickler!

Are the slides from this presentation available anywhere?

The UVVM forum seems to be quite silent and deserted. If the UVVM is being used so much, where do people post all the questions?

Is there any detailed comparison between UVVM, OSVVM and VUnit anywhere?

This is very cool! I have two questions: - Can it be ported to a PCB design with off-the-shelf components with reasonable price? - Can the memory/update algorithm part be handled on a PC's CPU/GPU then communicated to the board via USB? (to reduce board complexity)

This is amazing what Tim has developed. CACE makes life of analog designers much easier to validate their designs and build confidence before tapeout.

Availability of IHP rf pdk in open-source ecosystem will be a big boost. Looking forward eagerly to using it for some RF stuff.

Wow this is super useful!

xkcd 927

Looks useful!

Epic

First

🎉🎉🎉🎉🎉 YEAH!!!!!!!!!!!!!!!!!!!!

Bravo! 🎉

Thanks for having me, @FOSSiFoundation!

That whole conference was very informative and great fun! Thanks to all those who came and to FOSSi Foundation for setting it up and also giving those who couldn't be there the opportunity to see the talks, too, with these videos. I hope to have some more cool stuff on the analog stuff in the near future and hopefully something interesting for you next year :)

This sounds interesting! wanna give it a try

Nice work!

So this is for folks who doesn’t know SV?

Hiii, i have some doubts in bluespec. Can u help me

I dont want to the the man, I WANT TO SEE THE PRESENTATION :LKJDSAF:JLAJDSKF

27:20 To stay in the spirit of 24h-no-humans-in-loop, have you considered having the place-and-route tool automatically send an email asking Matt to do a better job as soon as routing is done, so the user doesn't need to?

Any updates to this? For example, I understand migen->nMigen has become Amaranth HDL.. but any thoughts how it compares to Chisel or Spinal HDL? Or for building SoCs.. LambdaSoc (Amaranth HDL) vs LiteX (m-labs or whitequark's Migen/MiSoc)? I'm looking at writing a custom AMBA ABH-Lite slave device, and glue them together with pre-existing components (litescope, ValentyUSB, minerva or VexRiscV) on a Trenz SMF2000 board.

Awesome presentation! I just got an XUP-P3R myself and I'll definitely give this a shot.

how can i use these filter in a python scripts?

I'd be curious to hear which companies use CocoTB. I've used it for some projects here and there because it makes building models very easy, but I'm yet to see/hear companies use it on their own designs.

Better over matlab FDA

We have been using it and loving it we will not go back to SV tbs

Very very good initiative for VLSI aspirants like me, As a student of ECE, it's very helpful. My earnest request to the makers of OPENROAD please make proper tutorial videos. It will be very helpful for us.

Cocotb is a game changer! Can't think about going back to SV or VHDL testbenches..

Great questions here - thanks for the interest, I will address them soon via social media posts/blogs. Great job Satinder Ji!

how is these not getting more views

Great project, great talk! Where did you get your PCB assembled?

crazy🎉

How is it possible (5:36) that 28nm costs 13000 US for 1mm^2? An iPhone Apple A15 or whatever in nm5 would cost like 100k US one chip? Those chips are bigger than 1mm?

Thanks for that video. I remember years ago while i wrote my bachelor thesis (computer science) I had first experiences with fpga and vivado. It TOOK me months to understand what is actually going on. I really had the impression I am dumb AF. But yeah the learning curve is extremely step. While I write this command yosys is running in the background and its so much easier to do stuff, its the real deal. But yeah I agree, simulation is not enough you need to implement your design. During my master thesis I had a bug that just appeared on the fgpa but not simulation, it took me 2 months to figure out this bug, it was insane. I ignored the vivado warning and missed that a latch was inferred... Beginner mistake

Didn't bother to include VHDL, lowest common denominator as usual.

So, does open road completely run on CPUs? Is there any focus on multi core CPUs, or GPUs to reduce the run time?