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FOSSi Foundation
United Kingdom
Приєднався 14 жов 2015
The FOSSi Foundation exists to promote and protect the open source silicon chip movement. It actively encourages the community’s growth and is helping to maintain the open spirit of the movement, through events, educational programmes and working groups. With an international membership of experts from academia and industry, it supports new open source initiatives and collaborations - offering free advice to governments and policy makers, corporations, academics and hobbyists. As a not-for profit organisation, the foundation is independent of any commercial interests and acts as a steward in support of open source projects which broadly benefit the open source silicon community. FOSSi is an acronym for Free and Open Source Silicon.
On this UA-cam channel, we collect videos from various talks and conferences we organize, showcasing the variety, ingenuity, and technical excellence of the Free and Open Source Silicon community.
On this UA-cam channel, we collect videos from various talks and conferences we organize, showcasing the variety, ingenuity, and technical excellence of the Free and Open Source Silicon community.
"Accelerating Hardware Design with Custom GPTs" - Prakash Shvetank (Latch_2024)
Prakash Shvetank
fossi-foundation.org/latch-up/2024
The stagnation of Moore's Law and Dennard scaling threatens the pace of technological innovation while also escalating the cost of hardware design and development. Artificial Intelligence (AI) emerges as a pivotal solution to transcend these limitations. This talk proposes and demonstrates interfacing CFU Playground, a full-stack open-source framework for ultra-low power ML accelerator design, with CustomGPTs from OpenAI. By leveraging GenAI to accelerate hardware design, we can reduce development costs and introduce a new era of efficiency and innovation in chip design.
The FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon.
Latch-Up: a weekend of presentations and networking for the open source silicon community, much like its European sister conference ORConf.
Produced by NDV: ua-cam.com/channels/Q7dFBzZGlBvtU2hCecsBBg.html
OpenHardware
Fri Apr 19 18:29:52 2024 at VenCaf
fossi-foundation.org/latch-up/2024
The stagnation of Moore's Law and Dennard scaling threatens the pace of technological innovation while also escalating the cost of hardware design and development. Artificial Intelligence (AI) emerges as a pivotal solution to transcend these limitations. This talk proposes and demonstrates interfacing CFU Playground, a full-stack open-source framework for ultra-low power ML accelerator design, with CustomGPTs from OpenAI. By leveraging GenAI to accelerate hardware design, we can reduce development costs and introduce a new era of efficiency and innovation in chip design.
The FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon.
Latch-Up: a weekend of presentations and networking for the open source silicon community, much like its European sister conference ORConf.
Produced by NDV: ua-cam.com/channels/Q7dFBzZGlBvtU2hCecsBBg.html
OpenHardware
Fri Apr 19 18:29:52 2024 at VenCaf
Переглядів: 306
Відео
OSHHISS Open Source for Hybrid Hetrogenous Integrated Semiconductor Systems
Переглядів 913 місяці тому
John Goodenough fossi-foundation.org/latch-up/2024 CTA for collaboration for Open source hardware design patterns and tools for Low Cost Hybrid Heterogeneous Systems: integration of sensor, power switch power amp The FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon. Latch-Up: a weekend of presentations and networking for the open source sili...
"ABC: The Way It Should Have Been Designed" - Alan Mishchenko (Latch_2024)
Переглядів 5833 місяці тому
Alan Mishchenko fossi-foundation.org/latch-up/2024 Almost two decades ago, in September 2005, the first public version of ABC was released. It featured technology-independent synthesis using DAG-aware rewriting, technology mapping for standard cells and lookup tables, and simple combinational equivalence checking, all based on the And-Inverter Graphs (AIG) data-structure used to unify the compu...
"UMI: Universal Memory Interface" - Andreas Olofsson (Latch_2024)
Переглядів 4403 місяці тому
Andreas Olofsson fossi-foundation.org/latch-up/2024 Standardized bus architectures like Wishbone and AXI have helped designers construct complex systems from a basic set of interface compliant building blocks ("IPs"). The bus approach has worked well for decades, but requires a large number of wires to implement and does't scale particularly well. For PCB design and System-In-Package design, th...
"From an Open-Source ISA to Open-Source HW to Open-Source Silicon" - Luca Bertaccini (Latch_2024)
Переглядів 3353 місяці тому
Luca Bertaccini fossi-foundation.org/latch-up/2024 In this talk, we will provide a comprehensive overview of the PULP platform's open-source activities and roadmap: starting from an open-source instruction set architecture (ISA) to open-source hardware IPs to the employment of open-source EDA tools. In addition, we will cover the benefits we experienced thanks to this open-source model, the cha...
"Transparent Checkpointing for Fault Tolerance in RISC-V" - Aayushi Gautam (Latch_2024)
Переглядів 843 місяці тому
Aayushi Gautam fossi-foundation.org/latch-up/2024 DMTCP (Distributed MultiThreaded Checkpointing) is a powerful open-source tool designed to facilitate the checkpointing and restart of parallel and distributed applications. It operates by intercepting system calls, capturing the entire process state and creating a restorable checkpoint. This enables users to save and restore the execution state...
Sonata: A development platform to enable exploring the use of CHERI for embedded applications
Переглядів 1593 місяці тому
Hugo McNally fossi-foundation.org/latch-up/2024 "A huge number of security vulnerabilities can be mitigated by enforcing memory safety. In tandem to writing new code in memory safe languages, CHERI technologies can be used in hardware to enforce memory safety in existing codebases written in unsafe languages such as C and C . Sonata provides a development platform designed to bring CHERI techno...
"Where Community Powers Innovation" - Mohamed Kassem (Latch_2024)
Переглядів 793 місяці тому
Mohamed Kassem fossi-foundation.org/latch-up/2024 The FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon. Latch-Up: a weekend of presentations and networking for the open source silicon community, much like its European sister conference ORConf. Produced by NDV: ua-cam.com/channels/Q7dFBzZGlBvtU2hCecsBBg.html OpenHardware Fri Apr 19 18:35:26 2...
"Open source RTL verification with Verilator" - Karol Gugala (Latch_2024)
Переглядів 7493 місяці тому
Karol Gugala fossi-foundation.org/latch-up/2024 This presentation follows up on the [ORConf 2023](orconf.org/) [UVM support overview talk](orconf.org/#open-source-design-testing-and-verification-with-uvm-and-verilator) and discusses Antmicro's work towards enabling constrained randomization in Verilator, another important milestone on the road towards full open source UVM support. Ultimately, t...
Architecture 2.0: Toward Open Source Foundation Models and Datasets for Hardware Design
Переглядів 1543 місяці тому
Vijay Janapa Reddi, Shvetank Prakash fossi-foundation.org/latch-up/2024 Designing specialized hardware is challenging due to high costs, long development cycles, and error risks. Architecture 2.0 aims to address these challenges and democratize hardware design by leveraging open source foundation models, hardware-oriented datasets, and generative AI. This talk explores the challenges and opport...
"Chisel 6 and beyond" - Jack Koenig (Latch_2024)
Переглядів 4253 місяці тому
Jack Koenig fossi-foundation.org/latch-up/2024 Chisel (formerly Chisel 3) is a hardware generator language embedded in the Scala general-purpose programming language. It empowers hardware designers to write reusable hardware generators to improve the productivity of design. At Latch Up last year, we discussed the new MLIR FIRRTL compiler and how that would enable more rapid feature development ...
"Zeno: An Open-Source Scalable Capability-Based Secure Architecture" - Alan Ehret (Latch_2024)
Переглядів 1093 місяці тому
Alan Ehret fossi-foundation.org/latch-up/2024 The FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon. Latch-Up: a weekend of presentations and networking for the open source silicon community, much like its European sister conference ORConf. Produced by NDV: ua-cam.com/channels/Q7dFBzZGlBvtU2hCecsBBg.html OpenHardware Fri Apr 19 18:27:21 2024 ...
"Attempts to design hardware using dafny" - Ben Reynwar (Latch_2024)
Переглядів 833 місяці тому
Ben Reynwar fossi-foundation.org/latch-up/2024 I'm currently trying to use dafny (a proof assistant backed by a SAT solver) to try to design hardware and prove properties about it. The FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon. Latch-Up: a weekend of presentations and networking for the open source silicon community, much like its Eur...
"Teaching Modern EDA using a Tapeout-Centric University Course" - Anish Singhani (Latch_2024)
Переглядів 3633 місяці тому
Anish Singhani fossi-foundation.org/latch-up/2024 In this presentation, we will discuss our progress in developing and operating (for the past four semesters) a tapeout-centric course at Carnegie Mellon University to teach students about the open-source EDA landscape and give them hands-on experience working with open-source tooling. The access to high-quality visualization tools, open standard...
"Tiny Tapeout: custom silicon open to all" - Pat Deegan (Latch_2024)
Переглядів 1,5 тис.3 місяці тому
Pat Deegan fossi-foundation.org/latch-up/2024 Tiny Tapeout is an educational project that makes it easier and cheaper than ever to get your digital designs manufactured on a real chip, and it's capabilities have been growing in leaps and bounds: speed, analog support, so many goodies. We'll walk through the process, touch on how it all works and explore the possibilities. The FOSSi Foundation i...
IHP Open Source PDK: Announcement, Setup, Current State and Experiences, and look ahead
Переглядів 5673 місяці тому
IHP Open Source PDK: Announcement, Setup, Current State and Experiences, and look ahead
"CACE Study: Open source analog and mixed-signal design flow" - Tim Edwards (Latch_2024)
Переглядів 3663 місяці тому
"CACE Study: Open source analog and mixed-signal design flow" - Tim Edwards (Latch_2024)
"RF Front-end receiver design for 2.4GH/5GHz WiFi application" - Jabeom Koo (Latch_2024)
Переглядів 2253 місяці тому
"RF Front-end receiver design for 2.4GH/5GHz WiFi application" - Jabeom Koo (Latch_2024)
"Beyond EDA lies Edalize" - Olof Kindgren (Latch_2024)
Переглядів 8833 місяці тому
"Beyond EDA lies Edalize" - Olof Kindgren (Latch_2024)
A History of TL-Verilog Google Summer of Code Projects under FOSSi Foundation
Переглядів 2323 місяці тому
A History of TL-Verilog Google Summer of Code Projects under FOSSi Foundation
"Open Source Hardware: Hacking Silicon for Fun (instead of profit)" - Troy Benjegerdes (Latch_2024)
Переглядів 1073 місяці тому
"Open Source Hardware: Hacking Silicon for Fun (instead of profit)" - Troy Benjegerdes (Latch_2024)
"Switchboard: Calling All Hardware Models" - Steven Herbst (Latch_2024)
Переглядів 953 місяці тому
"Switchboard: Calling All Hardware Models" - Steven Herbst (Latch_2024)
"Spade: An HDL Inspired By Modern Software Languages" - Frans Skarman (Latch_2024)
Переглядів 5103 місяці тому
"Spade: An HDL Inspired By Modern Software Languages" - Frans Skarman (Latch_2024)
"HDLAgent, Enhancing Hardware Language in the age of LLMs" - Jose Renau (Latch_2024)
Переглядів 743 місяці тому
"HDLAgent, Enhancing Hardware Language in the age of LLMs" - Jose Renau (Latch_2024)
"PyHDL-IF: An Easy-to-Use Python/HDL Cross-Calling Interface" - Matt Ballance (Latch_2024)
Переглядів 1883 місяці тому
"PyHDL-IF: An Easy-to-Use Python/HDL Cross-Calling Interface" - Matt Ballance (Latch_2024)
"Open-source resources for learning the Bluespec HL-HDLs" - Rishiyur Nikhil (Latch_2024)
Переглядів 1063 місяці тому
"Open-source resources for learning the Bluespec HL-HDLs" - Rishiyur Nikhil (Latch_2024)
"Giving Students A Byte of Open-Source: Advancing Hardware Education" - Ethan Sifferman (Latch_2024)
Переглядів 2093 місяці тому
"Giving Students A Byte of Open-Source: Advancing Hardware Education" - Ethan Sifferman (Latch_2024)
"Riding The Wave: Building Wave Pipelines in FPGAs" - Rice Shelley (Latch_2024)
Переглядів 2843 місяці тому
"Riding The Wave: Building Wave Pipelines in FPGAs" - Rice Shelley (Latch_2024)
MRPHS: Enabling Transaction-level Deductive Formal Verification Through PDVL
Переглядів 473 місяці тому
MRPHS: Enabling Transaction-level Deductive Formal Verification Through PDVL
"Artifact Evaluation for the Field Programmable Gate Array Community" - Miriam Leeser (Latch_2024)
Переглядів 1123 місяці тому
"Artifact Evaluation for the Field Programmable Gate Array Community" - Miriam Leeser (Latch_2024)
Amazing, thanks for bringing this topic to the light and discussing on it!
Possible to re-upload without the picture flashing? Thanks
One of the best accelerate NIC hardware on FPGA presentation I've heard for free
Where can I get a Sonata board?
Can SystemRDl support SystemC Verifcatoin Constraint from the SCV package? And then generate the SystemC header file including the constraint where the registers are described as Struct or Classes?
Boss, Your videos are very good, but please rename them with correct order.
Wonderful stuff!
your research is important to keep us not being enslaved remember we need a open source standard to have a new monetary system that's not controlled by the world Elites
I trying to find Renode Emu Tutorial
This is so cool. I had actually read that very paper on wave pipelining, but didn't consider it practical (for all the reasons you cite). That fact you pulled it off and on an FPGA to boot, is impressive. Re. the audience comment: self timed logic is interesting too, but is completely different; wave pipelining is overhead-free, where as self-timed logic has buffers for each "wave". The main difference from synchronous is that the clock is effectively local to each stage (which has its own pros and cons).
Really a nice presentation. But the demo seems not work through the command provided.
This looks a lot like Cadence ADE Assembler. It seems like I'm going to have to take some time and do some analog/mixed-signal design with the open tools!
Great presentation by the tickler!
Are the slides from this presentation available anywhere?
The UVVM forum seems to be quite silent and deserted. If the UVVM is being used so much, where do people post all the questions?
Is there any detailed comparison between UVVM, OSVVM and VUnit anywhere?
This is very cool! I have two questions: - Can it be ported to a PCB design with off-the-shelf components with reasonable price? - Can the memory/update algorithm part be handled on a PC's CPU/GPU then communicated to the board via USB? (to reduce board complexity)
This is amazing what Tim has developed. CACE makes life of analog designers much easier to validate their designs and build confidence before tapeout.
Availability of IHP rf pdk in open-source ecosystem will be a big boost. Looking forward eagerly to using it for some RF stuff.
Wow this is super useful!
xkcd 927
Looks useful!
Epic
First
🎉🎉🎉🎉🎉 YEAH!!!!!!!!!!!!!!!!!!!!
Bravo! 🎉
Thanks for having me, @FOSSiFoundation!
That whole conference was very informative and great fun! Thanks to all those who came and to FOSSi Foundation for setting it up and also giving those who couldn't be there the opportunity to see the talks, too, with these videos. I hope to have some more cool stuff on the analog stuff in the near future and hopefully something interesting for you next year :)
Is there a Github link for your open source design? Thanks
This sounds interesting! wanna give it a try
Nice work!
So this is for folks who doesn’t know SV?
Hiii, i have some doubts in bluespec. Can u help me
I dont want to the the man, I WANT TO SEE THE PRESENTATION :LKJDSAF:JLAJDSKF
27:20 To stay in the spirit of 24h-no-humans-in-loop, have you considered having the place-and-route tool automatically send an email asking Matt to do a better job as soon as routing is done, so the user doesn't need to?
Any updates to this? For example, I understand migen->nMigen has become Amaranth HDL.. but any thoughts how it compares to Chisel or Spinal HDL? Or for building SoCs.. LambdaSoc (Amaranth HDL) vs LiteX (m-labs or whitequark's Migen/MiSoc)? I'm looking at writing a custom AMBA ABH-Lite slave device, and glue them together with pre-existing components (litescope, ValentyUSB, minerva or VexRiscV) on a Trenz SMF2000 board.
Awesome presentation! I just got an XUP-P3R myself and I'll definitely give this a shot.
how can i use these filter in a python scripts?
I'd be curious to hear which companies use CocoTB. I've used it for some projects here and there because it makes building models very easy, but I'm yet to see/hear companies use it on their own designs.
Better over matlab FDA
We have been using it and loving it we will not go back to SV tbs
Very very good initiative for VLSI aspirants like me, As a student of ECE, it's very helpful. My earnest request to the makers of OPENROAD please make proper tutorial videos. It will be very helpful for us.
Cocotb is a game changer! Can't think about going back to SV or VHDL testbenches..
Great questions here - thanks for the interest, I will address them soon via social media posts/blogs. Great job Satinder Ji!
how is these not getting more views
I just made it public this afternoon, so I bet there will be much more soon 😊
Great project, great talk! Where did you get your PCB assembled?
Maybe PCBWay? They are suitable for prototyping orders.
crazy🎉
How is it possible (5:36) that 28nm costs 13000 US for 1mm^2? An iPhone Apple A15 or whatever in nm5 would cost like 100k US one chip? Those chips are bigger than 1mm?
This is very low volume, multi project wafer. You share the mask cost and get a few dozen chips.
@@stefanwallentowitz7832 Ok I see but its still insane that apparently if you mass order your price per chip is x/1000000?
Thanks for that video. I remember years ago while i wrote my bachelor thesis (computer science) I had first experiences with fpga and vivado. It TOOK me months to understand what is actually going on. I really had the impression I am dumb AF. But yeah the learning curve is extremely step. While I write this command yosys is running in the background and its so much easier to do stuff, its the real deal. But yeah I agree, simulation is not enough you need to implement your design. During my master thesis I had a bug that just appeared on the fgpa but not simulation, it took me 2 months to figure out this bug, it was insane. I ignored the vivado warning and missed that a latch was inferred... Beginner mistake
Didn't bother to include VHDL, lowest common denominator as usual.
So, does open road completely run on CPUs? Is there any focus on multi core CPUs, or GPUs to reduce the run time?